Agemixer (07:21:29)
..which then leads into more hardware to get solved like that xD the syncing to c64 reads of course. the 1MHz line must be read, and once in 22 cycles it should reset the counters itself.

Agemixer (07:18:01)
just read the ever counting counter into eternity... and fixup the delta values later. Problem! The c64-wise 22 cycles must be then hardcoded to the sampler device somehow. wellwell. 2 extra counters needed. and the first initian reset line of course

Agemixer (07:14:26)
how to no reset need? Oh yes! no resets at all.

Agemixer (07:13:23)
if cia no need reset then theres a chance for loop nicely at 44kHz (inx, bne for loop of 256 samples)

Agemixer (07:11:14)
22 cycles... no advance, and only speedcode... barely 44 kHz. Hmmz!!

Agemixer (07:10:20)
lda #n sta CIAreset lda CIAsmp sta samplehi,x lda userport sta samplelo,x

Agemixer (07:02:54)
but could be that normal bc547 transistor would be enough even if it "leaks" just a tad bit

DennyItaly (07:01:57)
Agemixer o/

Agemixer (07:00:34)
and kinda require FETs for up/down powering. the RC that strives to the input levels.

Agemixer (06:57:38)
just in theory it "boosts" to kinda 256 MHz instead of 1MHz for the first bits to be read, but instead, this is made the analog way.

Teetow (Johan Lars Althoff)

Teo

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